A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes of various materials, e.g., metals, semiconductors and insulators. Each layer of shapes, also known as mask levels or mask layers, may be created or printed optically through well known photolithographic exposure and development steps. Typical such patterning steps may include, for example, etching, dopant implanting and material deposition. Each layer is stacked or overlaid precisely on a prior layer and patterned to form the shapes that define devices (e.g., Field Effect Transistors (FETs)) and connect the devices into circuits.
In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, the layers are formed on a wafer to form the devices on a surface of the wafer, e.g., a silicon surface layer of a Silicon On Insulator (SOI) wafer. A simple FET is formed by the intersection of two rectangles, a gate layer rectangle on a rectangular silicon island formed from the silicon surface layer. In a typical IC chip each individual FET has physical characteristics that depend, primarily, on intersecting shapes on these two layers. FET current, for example depends on device length and width. Device width may be set by the underlying island, which is a thin oxide/diffusion shape; and device length may be set by the uppermost gate shape, usually a polysilicon line crossing the island, with the width of the line determining the device length.
Normally, a chip designer creates an electrical and/or logic representation of a new circuit that is converted to a chip/circuit layout, e.g., using a general purpose computer, during what is commonly known as physical design. The designer uses device models, based on process parameters and physical structures that are extracted from the design, to demonstrate design performance. Typical such models include, for example, complex mathematical current models for each device that predict whether a particular design is meeting design goals. Once the designer has demonstrated design performance and functionality, the design is passed to physical design. In physical design, the circuit layout is generated and converted to data to print masks for printing chip layers. It is common to lose design shape fidelity printing from masks that have been created directly from the chip/circuit layout.
During printing each shape may be affected by or may affect other shapes in the vicinity. Non-linearities, associated with the various optical and resist patterning tools and materials, cause these shape interactions, which are commonly known as proximity effects. Consequently, physical design involves applying process biases to each shape in the particular chip/circuit layout in what is known as Optical Proximity Correction (OPC). These OPC process biases compensate for these proximity effects by intentionally distorting the drawn shapes such that the mask shapes print substantially as drawn. Using various modern lithographic refinements, e.g., Resolution Enhancement Technology (RET), the mask data from the OPC compensated shapes controls the mask making tool to print photolithographic masks. Finally, the masks are used to print the design pattern onto the wafer.
As mask shapes and spaces have shrunk with increases in technology density, proximity effects have become more prominent and OPC has become more complex. Typically, OPC modifies the drawn layout shapes, strategically adding/removing features. For example, what are known as “flares” and “hammer heads” may be placed at the end of lines to compensate for “line-end shortening” effects. What are called “serifs” may be attached at rectangular corners to compensate for “corner rounding” effects. These shapes are typically added using to formalized rules-based OPC methods or by the more modern Model Based OPC (MBOPC) methods.
In some cases OPC may be uniformly applied to a single shape, e.g., for two parallel lines on minimum pitch; in others, for example where multiple different adjacent shapes affect the same shape differently, OPC is more complex/rigorous. For example, OPC may be applied by dividing each shape edge into several segments. Then each individual segment is distorted or displaced to compensate for the proximity effects. The resulting mask and the associated RET step ensures that the layout drawn shapes are transferred to the silicon wafer with great fidelity. Depending upon the particular design, each of these layers may include several hundreds of millions, even billions, of mask shapes. Since proximity effects may vary from shape to shape, OPC complexity has increased the mask generation computational requirement significantly, requiring both more powerful computing resources and increasing the time required for OPC. This increases mask generation costs and, as a result, IC manufacturing costs as well as the cost of the ICs themselves.
Moreover, once physical design is complete and the masks have been fabricated, each photolithographic mask is used to print the layout pattern onto the semiconductor wafer, defining local wafer properties or one of the chip/circuit layers. If the residual proximity effects cause a single device to fail or match its design goal (e.g., device current falls short of its design current because of device length variations introduced from using too coarse OPC granularity), the circuit will not function as designed and the chip may fail to achieve overall design goals. Failing chips reduce yield and, consequently, also increase IC manufacturing costs as well as the cost of the ICs themselves.
Thus, there is a need for producing IC masks that accurately reflect circuit design intent without complicating the mask design such that computer resources become prohibitive.